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Top New Best Ask Show Jobs

Top New Best Ask Show Jobs

271.

Bitcoin arbitrage without market risk

github.com/butor

9 years ago

138 points

272.

RVVM – RISC-V Virtual Machine

github.com/lekkit

5 years ago

129 points

273.

Show HN: CLI that spots fake GitHub stars, risky dependencies and licence traps

github.com/m-ahmed-elbeskeri

a year ago

122 points

274.

A FPGA friendly 32 bit RISC-V CPU implementation

github.com/SpinalHDL

a year ago

121 points

275.

IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device

github.com/BrunoLevy

6 years ago

119 points

276.

ZipCPU – A small, lightweight, RISC soft core in Verilog

github.com/ZipCPU

7 years ago

118 points

277.

Hallucination Risk Calculator

github.com/leochlon

9 months ago

118 points

278.

T1: A RISC-V Vector processor implementation

github.com/chipsalliance

a year ago

117 points

279.

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V

github.com/roscopeco

3 months ago

115 points

280.

De-risking custom technology projects: 18F technology budgeting guide

6 years ago

114 points

281.

Jupiter: RISC-V Assembler and Runtime Simulator

github.com/andrescv

7 years ago

112 points

282.

NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM

github.com/sipeed

2 years ago

111 points

283.

Leaving Spellcheck Enabled Is a Privacy Risk (2016)

github.com/signalapp

6 years ago

107 points

284.

Show HN: IDE for Learning RISC-V

github.com/TheThirdOne

7 years ago

105 points

285.

An FPGA-friendly 32-bit RISC-V CPU implementation

github.com/SpinalHDL

9 years ago

102 points

286.

VeriGPU: GPU in Verilog loosely based on RISC-V ISA

github.com/hughperkins

4 years ago

101 points

287.

Open-source soft-core RISC-V SoC with gdb support

github.com/stnolting

5 years ago

94 points

288.

Multiple Vulnerabilities in IBM Data Risk Manager

github.com/pedrib

6 years ago

88 points

289.

A minimal operating system (2K LOC) on QEMU and a RISC-V board

github.com/yhzhang0128

3 years ago

87 points

290.

SiFive open sources RISC-V chips

github.com/sifive

10 years ago

85 points

291.

QuantMath: Financial maths library for risk-neutral pricing and risk in Rust

github.com/MarcusRainbow

5 years ago

83 points

292.

Glacial – Microcoded RISC-V core designed for low FPGA resource utilization

github.com/brouhaha

5 years ago

peter_d_sherman

78 points

293.

ORCA – An implementation of RISC-V intended to target FPGAs

github.com/VectorBlox

10 years ago

77 points

294.

The Ice-V: a simple, compact RISC-V RV32I implementation in Silice

github.com/sylefeb

5 years ago

75 points

295.

Show HN: New RISC-V emulator for Computer Science education

github.com/gboncoffee

2 years ago

71 points

296.

Multiplix, operating system kernel for RISC-V and AArch64 SBCs

github.com/zyedidia

3 years ago

70 points

297.

Emuko: Fast RISC-V emulator written in Rust, boots Linux

github.com/wkoszek

4 months ago

70 points

298.

Mojo-V: Secret Computation for RISC-V

github.com/toddmaustin

7 months ago

66 points

299.

Show HN: A pipelined RISC-V processor written in VHDL

github.com/inforichland

11 years ago

65 points

300.

Click-V: A RISC-V emulator built with ClickHouse SQL

github.com/SpencerTorres

a year ago

64 points