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451.

Let Claude control your computer (at your own risk)

github.com/suitedaces

2 years ago

2 points

452.

Overmind – Identify the Blast Radius and Risks for Terraform Changes

github.com/overmindtech

2 years ago

2 points

453.

Go_emu: Go lang RISC-V 5 stage pipeline emulator

github.com/nobotro

2 years ago

2 points

454.

A simple superscalar out of order RISC-V (micro)processor

github.com/mathis-s

2 years ago

2 points

455.

Show HN: Research market trends or find companies by domain or risk exposure

searchsecdata.com

2 years ago

2 points

456.

Show HN: LowEndInsight – a “bus-factor” risk analysis tool

lowendinsight.dev

3 years ago

2 points

457.

No-MMU Linux Capable RISC-V SoC

github.com/regymm

4 years ago

2 points

458.

The CORE-V CVA6 is a RISC-V CPU capable of booting Linux

github.com/openhwgroup

4 years ago

2 points

459.

Packj runner flags risky/malicious NPM/PyPI/Ruby dependencies in your PRs

github.com/marketplace

4 years ago

2 points

460.

Rvscript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

4 years ago

2 points

461.

Adding newlib system calls to a bare-metal RISC-V platform

github.com/stnolting

4 years ago

2 points

462.

Ripes: Visual computer RISC-V architecture simulator and assembly code editor

github.com/mortbopet

4 years ago

2 points

463.

Show HN: Superscalar RISC-V CPU written in Clash

github.com/losfair

5 years ago

2 points

464.

Show HN: Xv6 OS port to Nezha D1 RISC-V board

github.com/michaelengel

5 years ago

2 points

465.

Show HN: DerzForth – Bare-metal Forth implementation for RISC-V

github.com/theandrew168

5 years ago

2 points

466.

Rvc – RISC-V in C / HLSL

github.com/PiMaker

5 years ago

2 points

467.

Conquest – Risk-like game written in Godot

github.com/argosopentech

5 years ago

2 points

468.

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support

github.com/stnolting

5 years ago

2 points

469.

Git by a Bus: Estimate unique and at-risk knowledge in your source code

github.com/tomheon

5 years ago

2 points

470.

RISC-V Instruction Set Simulator Built for Education

github.com/vmmc2

6 years ago

2 points

471.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

6 years ago

2 points

472.

Open source API to evaluate risk of Covid-19 contamination during a trip

github.com/thetreep

6 years ago

2 points

473.

RVScript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

6 years ago

2 points

474.

RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

github.com/rsd-devel

7 years ago

2 points

475.

LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline

github.com/lowRISC

7 years ago

peter_d_sherman

2 points

476.

De-risking custom technology projects

7 years ago

2 points

477.

RISC-V CPU with simple 5-stage in-order pipeline for FPGA

github.com/bluespec

8 years ago

2 points

478.

Method for an Optimised aNAlysis of Risks version 2.7.1 released

github.com/monarc-project

8 years ago

2 points

479.

MONARC introduces the Statement of Applicability module for your risk analysis

github.com/monarc-project

8 years ago

2 points

480.

Show HN: FireCaster – Predicting Urban Fire Risk in NYC

github.com/tzano

8 years ago

2 points