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481.

RISC-V Vector Primer

github.com/simplex-micro

5 months ago

4 points

482.

Calyx-riscv: RISCV Core written in Calyx

github.com/sgpthomas

2 years ago

4 points

483.

A concise example for learning assembly, linking and relocation

github.com/peiyuanix

3 years ago

4 points

484.

A minimal RISC-V bare metal program to print “Hello, RISC-V”

github.com/peiyuanix

3 years ago

4 points

485.

Jonesforth Port to RISC-V

github.com/jjyr

6 years ago

2 points

486.

Show HN: Porting RISCOF to a new RISC-V target

github.com/stnolting

4 years ago

youre_the_voice

2 points

487.

Porting OpenBSD to RISC-V ISA

github.com/MengshiLi

5 years ago

2 points

488.

Show HN: A small RISC-V Virtual Machine

github.com/bit-hack

6 years ago

2 points

489.

Port of (JavaScript version of) corewars8086 to RISC-V

github.com/westerndigitalcorporation

7 years ago

2 points

490.

RISC-V CPU in Chisel

github.com/ucb-bar

13 years ago

1 points

491.

Show HN: The C3 programming language (C alternative language)

github.com/c3lang

a year ago

175 points

492.

Ask HN: Examples of Microkernels?

4 years ago

80 points

493.

Vibe Code Warning – A personal casestudy

github.com/jackdoe

7 months ago

400 points

494.

github.com/mit-pdos

7 years ago

114 points

495.

RISC-V userspace emulator library

github.com/fwsGonzo

7 years ago

43 points

496.

github.com/mit-pdos

4 years ago

5 points

497.

RISC-V userspace emulator library

github.com/fwsGonzo

7 years ago

3 points

498.

How to make RISC-V Microcomputer using FPGA for programmer

github.com/horie-t

4 years ago

2 points

499.

Show HN: TCP Socket in RISC-V Assembly (RV64I)

github.com/triilman25

a year ago

4 points

500.

AOSP (Android 10) port to RISC-V

github.com/T-head-Semi

5 years ago

4 points

501.

Android 10 ported to RISC-V

github.com/T-head-Semi

5 years ago

2 points

502.

Show HN: rust-based kernel with asynchronous context switching

github.com/xiaoyang-sde

3 years ago

1 points

503.

Python RiscV Core

github.com/cjdrake

a year ago

2 points

504.

Educational OS Labs for RISC-V CPU

github.com/chyyuu

8 years ago

2 points

505.

An ex-ARM engineer critiques RISC-V

gist.github.com

6 years ago

350 points

506.

Verilog sources for Western Digital's open source RISC-V core

github.com/westerndigitalcorporation

7 years ago

320 points

507.

Computerraria: A fully compliant RISC-V computer inside Terraria

github.com/misprit7

3 years ago

289 points

508.

Open source RISC-V implemented from scratch in one night

github.com/darklife

8 years ago

272 points

509.

XiangShan – Open-source high performance RISC-V processor

github.com/OpenXiangShan

a year ago

270 points

510.

Open-source high-performance RISC-V processor

github.com/OpenXiangShan

3 years ago

262 points