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511.
▲
Computerraria: A fully compliant RISC-V computer inside Terraria
github.com/misprit7
41 comments
3 years ago
inickt
289 points
512.
▲
Open source RISC-V implemented from scratch in one night
github.com/darklife
109 comments
8 years ago
guigg
272 points
513.
▲
XiangShan – Open-source high performance RISC-V processor
github.com/OpenXiangShan
98 comments
a year ago
gjvc
270 points
514.
▲
Open-source high-performance RISC-V processor
github.com/OpenXiangShan
109 comments
3 years ago
burakemir
262 points
515.
▲
Lion: A formally verified, 5-stage pipeline RISC-V core
github.com/standardsemiconductor
81 comments
5 years ago
varbhat
241 points
516.
▲
Writing an OS in Rust to run on RISC-V
gist.github.com
72 comments
3 years ago
favourable
229 points
517.
▲
Ariane RISC-V CPU – An open source CPU capable of booting Linux
github.com/openhwgroup
34 comments
6 years ago
grlass
210 points
518.
▲
Open source RISC-V GPGPU
github.com/vortexgpgpu
58 comments
5 years ago
1ntEgr8
207 points
519.
▲
A tiny C header-only RISC-V emulator
github.com/cnlohr
22 comments
4 years ago
todsacerdoti
205 points
520.
▲
Octox: Unix-like OS in Rust inspired by xv6-riscv
github.com/o8vm
119 comments
3 years ago
o8vm
190 points
521.
▲
Show HN: RISC-V core written in 600 lines of C89
github.com/mnurzia
83 comments
3 years ago
mnurzia
190 points
522.
▲
Linux running inside a PDF file via a RISC-V emulator
github.com/ading2210
38 comments
a year ago
shantara
183 points
523.
▲
Ariane RISC-V CPU
github.com/pulp-platform
43 comments
8 years ago
nickik
171 points
524.
▲
Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU
github.com/gsmecher
38 comments
4 years ago
gsmecher
171 points
525.
▲
Fast RISC-V-based scripting back end for game engines
github.com/fwsGonzo
84 comments
2 years ago
fwsgonzo
159 points
526.
▲
A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)
github.com/ben-j-c
22 comments
3 months ago
signa11
154 points
527.
▲
Western Digital SweRV RISC-V Core
github.com/chipsalliance
59 comments
6 years ago
ch_sm
153 points
528.
▲
Ripes: Visual computer architecture simulator, assembly code editor for RISC-V
github.com/mortbopet
14 comments
3 years ago
ingve
151 points
529.
▲
LuaJIT PR: Add Support for RISC-V 64
github.com/LuaJIT
53 comments
2 years ago
ignota
146 points
530.
▲
RVVM – The RISC-V Virtual Machine
github.com/LekKit
65 comments
3 years ago
api
140 points
531.
▲
RVVM – RISC-V Virtual Machine
github.com/lekkit
16 comments
5 years ago
rvenjoyer
129 points
532.
▲
A FPGA friendly 32 bit RISC-V CPU implementation
github.com/SpinalHDL
54 comments
a year ago
_benj
121 points
533.
▲
IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device
github.com/BrunoLevy
46 comments
6 years ago
homarp
119 points
534.
▲
ZipCPU – A small, lightweight, RISC soft core in Verilog
github.com/ZipCPU
43 comments
7 years ago
eatonphil
118 points
535.
▲
T1: A RISC-V Vector processor implementation
github.com/chipsalliance
19 comments
a year ago
namanyayg
117 points
536.
▲
Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V
github.com/roscopeco
32 comments
3 months ago
noone_youknow
115 points
537.
▲
Jupiter: RISC-V Assembler and Runtime Simulator
github.com/andrescv
7 comments
7 years ago
eatonphil
112 points
538.
▲
NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM
github.com/sipeed
55 comments
2 years ago
rcarmo
111 points
539.
▲
Show HN: IDE for Learning RISC-V
github.com/TheThirdOne
30 comments
7 years ago
thethirdone
105 points
540.
▲
An FPGA-friendly 32-bit RISC-V CPU implementation
github.com/SpinalHDL
43 comments
9 years ago
Dolu
102 points
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