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31.

Verilog for all proposed RISC-V bitmanip instructions

github.com/riscv

7 years ago

3 points

32.

RISC-V journey thru containers and new projects

github.com/carlosedp

7 years ago

3 points

33.

Need Suggestions for Riscv CPU

github.com/SHAOWEICHEN000

a year ago

2 points

34.

Preliminary in-progress RISC-V "P" Extension

github.com/riscv

2 months ago

2 points

35.

RISC-V Architecture Profiles 0.5 (RVI20, RVA20 and RVA22) for Discussion

github.com/riscv

4 years ago

2 points

36.

ELF Reader in Pure Tcl

github.com/jbroll

5 years ago

2 points

37.

riscv-pk: RISC-V Proxy Kernel and Boot Loader

github.com/riscv

6 years ago

2 points

38.

New open source F# RISC-V ISA formal specification and CPU simulation

github.com/mrLSD

7 years ago

2 points

39.

Working draft of the proposed RISC-V V vector extension

github.com/riscv

2 years ago

1 points

40.

Concerns over mask register design in RISC-V Vector Extension v1.0

github.com/riscv

4 years ago

1 points

41.

Show HN: Random instruction generator for RISC-V processor verification

github.com/google

5 years ago

1 points

42.

F# RISC-V Instruction Set Formal Specification

github.com/mrLSD

7 years ago

1 points

43.

Application execution environment for statically-linked RISC-V ELF binaries

github.com/riscv

7 years ago

1 points

44.

RISC vs. Cores and SoCs

github.com/riscv

7 years ago

1 points

45.

Show HN: I integrated my from-scratch TCP/IP stack into the xv6-riscv OS

github.com/pandax381

10 months ago

147 points

46.

Show HN: Porting xv6 to HiFive Unmatched board

github.com/eyengin

5 months ago

26 points

47.

Show HN: Easier Setup for Stephen Marz's “RISC-V OS in Rust” Series

github.com/kaycebasques

3 years ago

3 points

48.

Project Oberon 2013 on RISC-V

github.com/solbjorg

6 years ago

140 points

49.

Show HN: Confidential computing for high-assurance RISC-V embedded systems

a year ago

103 points

50.

Porting OpenBSD to RISC-V Final Report (2020) [pdf]

github.com/MengshiLi

5 years ago

93 points

51.

RISC-V Vector Primer

github.com/simplex-micro

4 months ago

69 points

52.

Jonesforth Port to RISC-V

github.com/jjyr

5 years ago

66 points

53.

RiscVivid – An educational RISC-V simulator

github.com/unia-sik

4 years ago

14 points

54.

Show HN: Emacs-riscv – A RISC-V emulator written in Emacs Lisp

github.com/gongo

6 months ago

10 points

55.

Marss-Riscv: Micro-ARchitectural Full System Simulator for RISC-V

github.com/bucaps

7 years ago

GeorgeTirebiter

8 points

56.

RISC-V Vector Primer

github.com/simplex-micro

5 months ago

4 points

57.

Calyx-riscv: RISCV Core written in Calyx

github.com/sgpthomas

2 years ago

4 points

58.

A concise example for learning assembly, linking and relocation

github.com/peiyuanix

3 years ago

4 points

59.

A minimal RISC-V bare metal program to print “Hello, RISC-V”

github.com/peiyuanix

3 years ago

4 points

60.

Jonesforth Port to RISC-V

github.com/jjyr

6 years ago

2 points