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31.

Librpmi: A RISC-V Platform Management Interface protocol implementation

github.com/riscv-software-src

2 years ago

3 points

32.

Intel Labs darecreek: open-source RISC-V vector unit (currently under test)

github.com/IntelLabs

3 years ago

3 points

33.

Boom: A high-performance open source RISC-V core

github.com/riscv-boom

5 years ago

3 points

34.

Configuration object and YAML-based storage for Rails apps

github.com/RISCfuture

15 years ago

3 points

35.

Google RISCV-DV, An open-source instruction generator for RISC-V verification

github.com/google

6 years ago

3 points

36.

RISC-V Software Ecosystem Overview

github.com/v8-riscv

6 years ago

3 points

37.

List of RISC-V Cores, SoC platforms and SoC chips available

github.com/riscv

6 years ago

3 points

38.

A Tour of the RISC-V ISA Formal Specification

github.com/rsnikhil

7 years ago

3 points

39.

Verilog for all proposed RISC-V bitmanip instructions

github.com/riscv

7 years ago

3 points

40.

RISC-V journey thru containers and new projects

github.com/carlosedp

7 years ago

3 points

41.

Ruby Dropbox gem

github.com/riscfuture

16 years ago

3 points

42.

Need Suggestions for Riscv CPU

github.com/SHAOWEICHEN000

a year ago

2 points

43.

Excellent Project Documentation

github.com/RISCfuture

14 years ago

2 points

44.

Preliminary in-progress RISC-V "P" Extension

github.com/riscv

2 months ago

2 points

45.

RISC-V Architecture Profiles 0.5 (RVI20, RVA20 and RVA22) for Discussion

github.com/riscv

4 years ago

2 points

46.

Digital Signatures on Risc0

github.com/risc0

4 years ago

2 points

47.

ELF Reader in Pure Tcl

github.com/jbroll

5 years ago

2 points

48.

riscv-pk: RISC-V Proxy Kernel and Boot Loader

github.com/riscv

6 years ago

2 points

49.

New open source F# RISC-V ISA formal specification and CPU simulation

github.com/mrLSD

7 years ago

2 points

50.

Working draft of the proposed RISC-V V vector extension

github.com/riscv

2 years ago

1 points

51.

RISC Zero MCP Server: Run Trustless and Verifiable Agentic Workflows

github.com/ronantakizawa

10 months ago

1 points

52.

Concerns over mask register design in RISC-V Vector Extension v1.0

github.com/riscv

4 years ago

1 points

53.

Show HN: Random instruction generator for RISC-V processor verification

github.com/google

5 years ago

1 points

54.

F# RISC-V Instruction Set Formal Specification

github.com/mrLSD

7 years ago

1 points

55.

Application execution environment for statically-linked RISC-V ELF binaries

github.com/riscv

7 years ago

1 points

56.

RISC vs. Cores and SoCs

github.com/riscv

7 years ago

1 points

57.

Show HN: I integrated my from-scratch TCP/IP stack into the xv6-riscv OS

github.com/pandax381

10 months ago

147 points

58.

Show HN: Porting xv6 to HiFive Unmatched board

github.com/eyengin

5 months ago

26 points

59.

Show HN: Easier Setup for Stephen Marz's “RISC-V OS in Rust” Series

github.com/kaycebasques

3 years ago

3 points

60.

Project Oberon 2013 on RISC-V

github.com/solbjorg

6 years ago

140 points