HK
Heykuki News
Top
New
Best
Ask
Show
Jobs
Toggle theme
Top
New
Best
Ask
Show
Jobs
Request
571.
▲
Ask HN: Porting MIT CADR to RISC-V
discuss
4 months ago
lstevens14
8 points
572.
▲
Smol-GPU: A tiny RISC-V GPU built to teach modern GPU architecture
github.com/Grubre
discuss
a year ago
thunderbong
8 points
573.
▲
How to get started with Rust for RISC-V targets
github.com/ockam-network
discuss
5 years ago
__mrinal__
8 points
574.
▲
Linux on RISC-V on Arduino Uno
github.com/raspiduino
6 comments
3 years ago
jamesy0ung
7 points
575.
▲
Kilo editor ported to Forth for RISC-V
github.com/mcmenaminadrian
4 comments
2 years ago
00_NOP
7 points
576.
▲
Apple is adding Mach-O's riscv32 support to LLVM
github.com/llvm
1 comment
a year ago
MaskRay
7 points
577.
▲
D Apps for Apache NuttX RTOS and QEMU RISC-V
github.com/kassane
discuss
2 years ago
lupyuen
7 points
578.
▲
Muntjac: An open source, Linux capable, 64 bit RISCV core
github.com/lowRISC
discuss
4 years ago
gchadwick
7 points
579.
▲
Show HN: Bronzebeard – Minimal assembler for bare-metal RISC-V development
github.com/theandrew168
discuss
5 years ago
theandrew168
7 points
580.
▲
JuiceVM: Smallest RISC-V Virtual Machine that can run Linux mainline kernel
github.com/juiceRv
discuss
5 years ago
homarp
7 points
581.
▲
BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model
github.com/agra-uni-bremen
discuss
2 years ago
matt_d
6 points
582.
▲
CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
github.com/openhwgroup
discuss
3 years ago
rwmj
6 points
583.
▲
FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello
github.com/CTSRD-CHERI
discuss
5 years ago
lsllc
6 points
584.
▲
Flute: RISC-V CPU, simple 5-stage in-order pipeline
github.com/bluespec
discuss
7 years ago
EvgeniyZh
6 points
585.
▲
RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis
gist.github.com
5 comments
2 years ago
camel-cdr
5 points
586.
▲
Show HN: RISC-V Linux Terminal emulated via WASM
cartesi-machine.surge.sh
5 comments
3 years ago
edubart
5 points
587.
▲
Show HN: Brainfuck to RISC-V JIT compiler written in Zig
github.com/evelance
3 comments
a year ago
0x000xca0xfe
5 points
588.
▲
XiangShan (香山) is an open-source high-performance RISC-V processor project
github.com/OpenXiangShan
1 comment
5 years ago
DeathArrow
5 points
589.
▲
We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V
discuss
4 months ago
shrecshrec
5 points
590.
▲
MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs
github.com/cpldcpu
discuss
8 months ago
cpldcpu
5 points
591.
▲
RVVM: RISC-V Virtual Machine
github.com/LekKit
discuss
a year ago
api
5 points
592.
▲
Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code
github.com/micropython
discuss
2 years ago
rcarmo
5 points
593.
▲
Ettore: RISC-V virtual machine, written in Go
github.com/teivah
discuss
2 years ago
ingve
5 points
594.
▲
SERV – The SErial RISC-V CPU
github.com/olofk
discuss
3 years ago
RossBencina
5 points
595.
▲
A minimal operating system (2K LOC) on QEMU and a RISC-V board
github.com/yhzhang0128
discuss
3 years ago
Paul-Craft
5 points
596.
▲
core-v-wally: Configurable RISC-V Processor
github.com/openhwgroup
discuss
3 years ago
matt_d
5 points
597.
▲
Show HN: C++17 RISC-V RV32/64/128 userspace emulator library
github.com/fwsGonzo
discuss
4 years ago
fwsgonzo
5 points
598.
▲
T-Head/Alibaba RISC-V CPU cores open sourced
github.com/T-head-Semi
discuss
5 years ago
johndoe0815
5 points
599.
▲
OpenXiangShan, an open-source high-performance RISC-V processor project
github.com/OpenXiangShan
discuss
5 years ago
bctnry
5 points
600.
▲
Rvemu: RISC-V Emulator written in Rust (browser and CLI)
github.com/d0iasm
discuss
5 years ago
ansible
5 points
More