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631.
▲
Hangover: Running x86 programs with ARM/RISC-V Wine
github.com/AndreRH
discuss
2 years ago
anewhnaccount2
3 points
632.
▲
SoC RISC-V: An ASIC Implementation of the FEMTORV32
github.com/FelipeFFerreira
discuss
3 years ago
mariuz
3 points
633.
▲
Linux for Cheri RISC-V
github.com
discuss
4 years ago
fuklief
3 points
634.
▲
Mold 1.1 high-speed linker adds support for Link-Time Optimization and RISC-V
github.com/rui314
discuss
4 years ago
rui314
3 points
635.
▲
Vortex RISC-V Gpgpu
github.com/vortexgpgpu
discuss
5 years ago
hasheddan
3 points
636.
▲
BiRISC-V – 32-bit Superscalar RISC-V CPU
github.com/ultraembedded
discuss
5 years ago
kroggen
3 points
637.
▲
Juice VM is a small RISC-V virtual machine
github.com/juiceRv
discuss
5 years ago
doener
3 points
638.
▲
NERV – Naive Educational RISC-V Processor
github.com/YosysHQ
discuss
5 years ago
kasbah
3 points
639.
▲
BiRISC-V – 32-bit dual issue RISC-V CPU
github.com/ultraembedded
discuss
5 years ago
jhallenworld
3 points
640.
▲
Ripes: RISC-V instruction set architecture simulator and assembly code editor
github.com/mortbopet
discuss
6 years ago
MindGods
3 points
641.
▲
WASC: an efficient WebAssembly to RISC-V AOT compiler
github.com/mohanson
discuss
6 years ago
mohanson
3 points
642.
▲
Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA
github.com/mortbopet
discuss
6 years ago
lelf
3 points
643.
▲
PicoRV32 – A Size-Optimized RISC-V CPU
github.com/cliffordwolf
discuss
6 years ago
tosh
3 points
644.
▲
Show HN: C++ RISC-V userspace emulator
github.com/fwsGonzo
discuss
7 years ago
fwsgonzo
3 points
645.
▲
Ripes: A graphical 5-stage RISC-V pipeline simulator and assembly editor
github.com/mortbopet
discuss
7 years ago
signa11
3 points
646.
▲
Simulating a RISC-V CPU in Terraria
github.com/yfdyzjt
1 comment
2 days ago
stevefan1999
2 points
647.
▲
Chatassembler is a RISC-V assembler that's over 10 times faster than GCC
github.com/Slackadays
1 comment
a year ago
netr0ute
2 points
648.
▲
Show HN: An educational RISC-V IDE, RARS, releases v1.3
github.com/TheThirdOne
1 comment
7 years ago
thethirdone
2 points
649.
▲
Heimdall – config-driven RTL fuzzing harness for RISC-V on FPGA
github.com/Midstall
discuss
12 days ago
rosscomputerguy
2 points
650.
▲
Felix – Run x86 and x86-64 games on RISC-V Linux
github.com/OFFTKP
discuss
a year ago
sandreas
2 points
651.
▲
Go_emu: Go lang RISC-V 5 stage pipeline emulator
github.com/nobotro
discuss
2 years ago
hggh
2 points
652.
▲
A simple superscalar out of order RISC-V (micro)processor
github.com/mathis-s
discuss
2 years ago
camel-cdr
2 points
653.
▲
No-MMU Linux Capable RISC-V SoC
github.com/regymm
discuss
4 years ago
picture
2 points
654.
▲
The CORE-V CVA6 is a RISC-V CPU capable of booting Linux
github.com/openhwgroup
discuss
4 years ago
btdmaster
2 points
655.
▲
Rvscript: Fast RISC-V-based scripting back end for game engines
github.com/fwsGonzo
discuss
4 years ago
fwsgonzo
2 points
656.
▲
Adding newlib system calls to a bare-metal RISC-V platform
github.com/stnolting
discuss
4 years ago
just_like_you
2 points
657.
▲
Ripes: Visual computer RISC-V architecture simulator and assembly code editor
github.com/mortbopet
discuss
4 years ago
ingve
2 points
658.
▲
Show HN: Superscalar RISC-V CPU written in Clash
github.com/losfair
discuss
5 years ago
losfair
2 points
659.
▲
Show HN: Xv6 OS port to Nezha D1 RISC-V board
github.com/michaelengel
discuss
5 years ago
johndoe0815
2 points
660.
▲
Show HN: DerzForth – Bare-metal Forth implementation for RISC-V
github.com/theandrew168
discuss
5 years ago
theandrew168
2 points
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