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61.
▲
Project Oberon 2013 on RISC-V
github.com/solbjorg
43 comments
6 years ago
homarp
140 points
62.
▲
Show HN: Confidential computing for high-assurance RISC-V embedded systems
github.com/IBM
9 comments
a year ago
mrnoone
103 points
63.
▲
Porting OpenBSD to RISC-V Final Report (2020) [pdf]
github.com/MengshiLi
4 comments
5 years ago
todsacerdoti
93 points
64.
▲
RISC-V Vector Primer
github.com/simplex-micro
22 comments
4 months ago
oxxoxoxooo
69 points
65.
▲
Jonesforth Port to RISC-V
github.com/jjyr
8 comments
5 years ago
rwmj
66 points
66.
▲
Riscrithm – An intuitive RISC-V assembler and optimizer coded in Go
github.com/ghetea-patrick
13 comments
a month ago
patrick-ghetea
32 points
67.
▲
RiscVivid – An educational RISC-V simulator
github.com/unia-sik
discuss
4 years ago
nanope
14 points
68.
▲
Show HN: Emacs-riscv – A RISC-V emulator written in Emacs Lisp
github.com/gongo
discuss
6 months ago
gongo
10 points
69.
▲
Marss-Riscv: Micro-ARchitectural Full System Simulator for RISC-V
github.com/bucaps
1 comment
7 years ago
GeorgeTirebiter
8 points
70.
▲
Riscrithm (v1.1) – An intuitive RISC-V assembler and optimizer written in Go
github.com/ghetea-patrick
2 comments
20 days ago
patrick-ghetea
4 points
71.
▲
RISC-V Vector Primer
github.com/simplex-micro
discuss
5 months ago
mshockwave
4 points
72.
▲
Calyx-riscv: RISCV Core written in Calyx
github.com/sgpthomas
discuss
2 years ago
luu
4 points
73.
▲
A concise example for learning assembly, linking and relocation
github.com/peiyuanix
discuss
3 years ago
peiyuanix
4 points
74.
▲
A minimal RISC-V bare metal program to print “Hello, RISC-V”
github.com/peiyuanix
discuss
3 years ago
peiyuanix
4 points
75.
▲
Jonesforth Port to RISC-V
github.com/jjyr
1 comment
6 years ago
rwmj
2 points
76.
▲
Show HN: Porting RISCOF to a new RISC-V target
github.com/stnolting
discuss
4 years ago
youre_the_voice
2 points
77.
▲
Porting OpenBSD to RISC-V ISA
github.com/MengshiLi
discuss
5 years ago
gbrown_
2 points
78.
▲
Show HN: A small RISC-V Virtual Machine
github.com/bit-hack
discuss
6 years ago
bit-hack
2 points
79.
▲
Port of (JavaScript version of) corewars8086 to RISC-V
github.com/westerndigitalcorporation
discuss
7 years ago
harshreality
2 points
80.
▲
RISC-V CPU in Chisel
github.com/ucb-bar
discuss
13 years ago
electronous
1 points
81.
▲
Show HN: The C3 programming language (C alternative language)
github.com/c3lang
185 comments
a year ago
lerno
175 points
82.
▲
Ask HN: Examples of Microkernels?
79 comments
4 years ago
agomez314
80 points
83.
▲
Vibe Code Warning – A personal casestudy
github.com/jackdoe
313 comments
7 months ago
jackdoe
400 points
84.
▲
Xv6 for RISC-V
github.com/mit-pdos
8 comments
7 years ago
ingve
114 points
85.
▲
RISC-V userspace emulator library
github.com/fwsGonzo
4 comments
7 years ago
ingve
43 points
86.
▲
Xv6 for RISC-V
github.com/mit-pdos
discuss
4 years ago
tirrex
5 points
87.
▲
RISC-V userspace emulator library
github.com/fwsGonzo
discuss
7 years ago
ingve
3 points
88.
▲
How to make RISC-V Microcomputer using FPGA for programmer
github.com/horie-t
1 comment
4 years ago
teleforce
2 points
89.
▲
Show HN: TCP Socket in RISC-V Assembly (RV64I)
github.com/triilman25
discuss
a year ago
triilman
4 points
90.
▲
AOSP (Android 10) port to RISC-V
github.com/T-head-Semi
discuss
5 years ago
rwmj
4 points
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