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91.

Show HN: rust-based kernel with asynchronous context switching

github.com/xiaoyang-sde

3 years ago

1 points

92.

Python RiscV Core

github.com/cjdrake

a year ago

2 points

93.

Educational OS Labs for RISC-V CPU

github.com/chyyuu

8 years ago

2 points

94.

An ex-ARM engineer critiques RISC-V

gist.github.com

6 years ago

350 points

95.

Verilog sources for Western Digital's open source RISC-V core

github.com/westerndigitalcorporation

7 years ago

320 points

96.

Computerraria: A fully compliant RISC-V computer inside Terraria

github.com/misprit7

3 years ago

289 points

97.

Open source RISC-V implemented from scratch in one night

github.com/darklife

8 years ago

272 points

98.

XiangShan – Open-source high performance RISC-V processor

github.com/OpenXiangShan

a year ago

270 points

99.

Open-source high-performance RISC-V processor

github.com/OpenXiangShan

3 years ago

262 points

100.

Lion: A formally verified, 5-stage pipeline RISC-V core

github.com/standardsemiconductor

5 years ago

241 points

101.

Writing an OS in Rust to run on RISC-V

gist.github.com

3 years ago

229 points

102.

Ariane RISC-V CPU – An open source CPU capable of booting Linux

github.com/openhwgroup

6 years ago

210 points

103.

Open source RISC-V GPGPU

github.com/vortexgpgpu

5 years ago

207 points

104.

A tiny C header-only RISC-V emulator

github.com/cnlohr

4 years ago

205 points

105.

Octox: Unix-like OS in Rust inspired by xv6-riscv

github.com/o8vm

3 years ago

190 points

106.

Show HN: RISC-V core written in 600 lines of C89

github.com/mnurzia

3 years ago

190 points

107.

Linux running inside a PDF file via a RISC-V emulator

github.com/ading2210

a year ago

183 points

108.

Ariane RISC-V CPU

github.com/pulp-platform

8 years ago

171 points

109.

Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU

github.com/gsmecher

4 years ago

171 points

110.

Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

2 years ago

159 points

111.

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)

github.com/ben-j-c

3 months ago

154 points

112.

Western Digital SweRV RISC-V Core

github.com/chipsalliance

6 years ago

153 points

113.

Ripes: Visual computer architecture simulator, assembly code editor for RISC-V

github.com/mortbopet

3 years ago

151 points

114.

LuaJIT PR: Add Support for RISC-V 64

github.com/LuaJIT

2 years ago

146 points

115.

Shellfirm: Intercept risky patterns at the command line

github.com/kaplanelad

4 years ago

145 points

116.

RVVM – The RISC-V Virtual Machine

github.com/LekKit

3 years ago

140 points

117.

RVVM – RISC-V Virtual Machine

github.com/lekkit

5 years ago

129 points

118.

Show HN: CLI that spots fake GitHub stars, risky dependencies and licence traps

github.com/m-ahmed-elbeskeri

a year ago

122 points

119.

A FPGA friendly 32 bit RISC-V CPU implementation

github.com/SpinalHDL

a year ago

121 points

120.

IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device

github.com/BrunoLevy

6 years ago

119 points