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121.

T1: A RISC-V Vector processor implementation

github.com/chipsalliance

a year ago

117 points

122.

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V

github.com/roscopeco

3 months ago

115 points

123.

Jupiter: RISC-V Assembler and Runtime Simulator

github.com/andrescv

7 years ago

112 points

124.

NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM

github.com/sipeed

2 years ago

111 points

125.

Show HN: IDE for Learning RISC-V

github.com/TheThirdOne

7 years ago

105 points

126.

An FPGA-friendly 32-bit RISC-V CPU implementation

github.com/SpinalHDL

9 years ago

102 points

127.

VeriGPU: GPU in Verilog loosely based on RISC-V ISA

github.com/hughperkins

4 years ago

101 points

128.

Open-source soft-core RISC-V SoC with gdb support

github.com/stnolting

5 years ago

94 points

129.

A minimal operating system (2K LOC) on QEMU and a RISC-V board

github.com/yhzhang0128

3 years ago

87 points

130.

SiFive open sources RISC-V chips

github.com/sifive

10 years ago

85 points

131.

Glacial – Microcoded RISC-V core designed for low FPGA resource utilization

github.com/brouhaha

5 years ago

peter_d_sherman

78 points

132.

ORCA – An implementation of RISC-V intended to target FPGAs

github.com/VectorBlox

10 years ago

77 points

133.

The Ice-V: a simple, compact RISC-V RV32I implementation in Silice

github.com/sylefeb

5 years ago

75 points

134.

Show HN: New RISC-V emulator for Computer Science education

github.com/gboncoffee

2 years ago

71 points

135.

Multiplix, operating system kernel for RISC-V and AArch64 SBCs

github.com/zyedidia

3 years ago

70 points

136.

Emuko: Fast RISC-V emulator written in Rust, boots Linux

github.com/wkoszek

4 months ago

70 points

137.

Mojo-V: Secret Computation for RISC-V

github.com/toddmaustin

7 months ago

66 points

138.

Show HN: A pipelined RISC-V processor written in VHDL

github.com/inforichland

11 years ago

65 points

139.

Click-V: A RISC-V emulator built with ClickHouse SQL

github.com/SpencerTorres

a year ago

64 points

140.

Adding custom RISC-V instructions to an open-source rv32 SoC

github.com/stnolting

4 years ago

54 points

141.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

11 years ago

53 points

142.

Geohot/twitchcore: A RISC-V core, first in Python, then in Verilog, then on FPGA

github.com/geohot

5 years ago

51 points

143.

Show HN: I built a RISC-V emulator that runs DOOM

github.com/lalitshankarch

2 months ago

50 points

144.

Some Criticisms of RISC-V

gist.github.com

7 years ago

DyslexicAtheist

41 points

145.

Show HN: Libriscv – RISC-V userspace emulator library

github.com/fwsGonzo

4 years ago

40 points

146.

NEORV32: A tiny, embedded and free-of-charge open-source RISC-V SoC

github.com/stnolting

4 years ago

40 points

147.

Show HN: C++17 RISC-V RV32GC / RV64GC userspace emulator library

github.com/fwsGonzo

6 years ago

31 points

148.

128-bit RISC-V assembler

github.com/fwsGonzo

5 years ago

30 points

149.

RISC-V Sandboxing Library

github.com/libriscv

a year ago

25 points

150.

Run Linux in VRChat by emulating RISC-V in a GPU shader program

github.com/PiMaker

5 years ago

18 points