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241.

Rvscript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

4 years ago

2 points

242.

Adding newlib system calls to a bare-metal RISC-V platform

github.com/stnolting

4 years ago

2 points

243.

Ripes: Visual computer RISC-V architecture simulator and assembly code editor

github.com/mortbopet

4 years ago

2 points

244.

Show HN: Superscalar RISC-V CPU written in Clash

github.com/losfair

5 years ago

2 points

245.

Show HN: Xv6 OS port to Nezha D1 RISC-V board

github.com/michaelengel

5 years ago

2 points

246.

Show HN: DerzForth – Bare-metal Forth implementation for RISC-V

github.com/theandrew168

5 years ago

2 points

247.

Rvc – RISC-V in C / HLSL

github.com/PiMaker

5 years ago

2 points

248.

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support

github.com/stnolting

5 years ago

2 points

249.

RISC-V Instruction Set Simulator Built for Education

github.com/vmmc2

6 years ago

2 points

250.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

6 years ago

2 points

251.

RVScript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

6 years ago

2 points

252.

RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

github.com/rsd-devel

7 years ago

2 points

253.

LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline

github.com/lowRISC

7 years ago

peter_d_sherman

2 points

254.

RISC-V CPU with simple 5-stage in-order pipeline for FPGA

github.com/bluespec

8 years ago

2 points

255.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

11 years ago

2 points

256.

The NEORV32 RISC-V soft-core microcontroller

github.com/stnolting

5 years ago

1 points

257.

Imagine CUDA on RISC-V

github.com/NVIDIA

a year ago

1 points

258.

Show HN: rqlite, distributed DB built on SQLite, now runs on MIPS, RISC, PowerPC

github.com/rqlite

3 years ago

1 points

259.

Run FreeBSD/Aarch64 and FreeBSD/Riscv64 Images Under FreeBSD/Amd64

gist.github.com

4 years ago

1 points

260.

Can you hack this RISC-V?

6 years ago

1 points

261.

Fast RISC-V-based scripting backend for game engines

github.com/fwsGonzo

6 years ago

1 points

262.

Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA

github.com/mortbopet

6 years ago

1 points

263.

Wujian100_open RISC-V SoC

github.com/T-head-Semi

7 years ago

1 points

264.

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

github.com/westerndigitalcorporation

7 years ago

1 points

265.

Ucore os was ported on risc-v 32/64 CPU

github.com/chyyuu

8 years ago

1 points

266.

Ask HN: What weird technical scene are you fond/part of?

4 years ago

295 points

267.

Show HN: We built an 8-bit CPU as 2nd year EE students

github.com/c0rRupT9

8 days ago

108 points

268.

Launch HN: Tensil (YC S19) – Open-Source ML Accelerators

4 years ago

96 points

269.

Show HN: StringZilla v3 with C++, Rust, and Swift bindings, and AVX-512 and NEON

github.com/ashvardanian

2 years ago

15 points

270.

Show HN: Vpod – Tiny Linux sandbox running in WASM

github.com/capsulerun

6 days ago

12 points