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241.

Heimdall – config-driven RTL fuzzing harness for RISC-V on FPGA

github.com/Midstall

10 days ago

rosscomputerguy

2 points

242.

Felix – Run x86 and x86-64 games on RISC-V Linux

github.com/OFFTKP

a year ago

2 points

243.

Go_emu: Go lang RISC-V 5 stage pipeline emulator

github.com/nobotro

2 years ago

2 points

244.

A simple superscalar out of order RISC-V (micro)processor

github.com/mathis-s

2 years ago

2 points

245.

No-MMU Linux Capable RISC-V SoC

github.com/regymm

4 years ago

2 points

246.

The CORE-V CVA6 is a RISC-V CPU capable of booting Linux

github.com/openhwgroup

4 years ago

2 points

247.

Packj runner flags risky/malicious NPM/PyPI/Ruby dependencies in your PRs

github.com/marketplace

4 years ago

2 points

248.

Rvscript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

4 years ago

2 points

249.

Adding newlib system calls to a bare-metal RISC-V platform

github.com/stnolting

4 years ago

2 points

250.

Ripes: Visual computer RISC-V architecture simulator and assembly code editor

github.com/mortbopet

4 years ago

2 points

251.

Show HN: Superscalar RISC-V CPU written in Clash

github.com/losfair

5 years ago

2 points

252.

Show HN: Xv6 OS port to Nezha D1 RISC-V board

github.com/michaelengel

5 years ago

2 points

253.

Show HN: DerzForth – Bare-metal Forth implementation for RISC-V

github.com/theandrew168

5 years ago

2 points

254.

Rvc – RISC-V in C / HLSL

github.com/PiMaker

5 years ago

2 points

255.

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support

github.com/stnolting

5 years ago

2 points

256.

RISC-V Instruction Set Simulator Built for Education

github.com/vmmc2

6 years ago

2 points

257.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

6 years ago

2 points

258.

RVScript: Fast RISC-V-based scripting back end for game engines

github.com/fwsGonzo

6 years ago

2 points

259.

RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

github.com/rsd-devel

7 years ago

2 points

260.

LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline

github.com/lowRISC

7 years ago

peter_d_sherman

2 points

261.

RISC-V CPU with simple 5-stage in-order pipeline for FPGA

github.com/bluespec

8 years ago

2 points

262.

PicoRV32 – A Size-Optimized RISC-V CPU

github.com/cliffordwolf

11 years ago

2 points

263.

ImpactCheck – CLI to detect risky configuration changes before deploy

github.com/fede456

4 months ago

1 points

264.

The NEORV32 RISC-V soft-core microcontroller

github.com/stnolting

5 years ago

1 points

265.

Show HN: GodScore CI – a CI gate that blocks risky changes before production

github.com/willshacklett

5 months ago

1 points

266.

Imagine CUDA on RISC-V

github.com/NVIDIA

a year ago

1 points

267.

Show HN: rqlite, distributed DB built on SQLite, now runs on MIPS, RISC, PowerPC

github.com/rqlite

3 years ago

1 points

268.

Run FreeBSD/Aarch64 and FreeBSD/Riscv64 Images Under FreeBSD/Amd64

gist.github.com

4 years ago

1 points

269.

Can you hack this RISC-V?

6 years ago

1 points

270.

Fast RISC-V-based scripting backend for game engines

github.com/fwsGonzo

6 years ago

1 points