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1.

A FPGA friendly 32 bit RISC-V CPU implementation

github.com/SpinalHDL

a year ago

121 points

2.

An FPGA-friendly 32-bit RISC-V CPU implementation

github.com/SpinalHDL

9 years ago

102 points

3.

SpinalHDL: Write Scala, Get VHDL/Verilog

github.com/SpinalHDL

9 years ago

3 points

4.

SpinalHDL – A high level hardware description language based on Scala

github.com/SpinalHDL

4 years ago

2 points

5.

Advent of Code with SpinalHDL

github.com/fayalalebrun

3 years ago

1 points

6.

Show HN: Simten – design hardware in TypeScript and simulate it in the browser

13 days ago

3 points