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331.

Show HN: Bronzebeard – Minimal assembler for bare-metal RISC-V development

github.com/theandrew168

5 years ago

7 points

332.

JuiceVM: Smallest RISC-V Virtual Machine that can run Linux mainline kernel

github.com/juiceRv

5 years ago

7 points

333.

BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model

github.com/agra-uni-bremen

2 years ago

6 points

334.

CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux

github.com/openhwgroup

3 years ago

6 points

335.

De-risking custom technology projects (18F)

5 years ago

thibaut_barrere

6 points

336.

FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello

github.com/CTSRD-CHERI

5 years ago

6 points

337.

github.com/mnquants

5 years ago

6 points

338.

Flute: RISC-V CPU, simple 5-stage in-order pipeline

github.com/bluespec

7 years ago

6 points

339.

RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis

gist.github.com

2 years ago

5 points

340.

Show HN: RISC-V Linux Terminal emulated via WASM

cartesi-machine.surge.sh

3 years ago

5 points

341.

Ask HN: Why some stories rise while others go unnoticed?

9 years ago

5 points

342.

Show HN: Brainfuck to RISC-V JIT compiler written in Zig

github.com/evelance

a year ago

5 points

343.

XiangShan (香山) is an open-source high-performance RISC-V processor project

github.com/OpenXiangShan

5 years ago

5 points

344.

We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V

4 months ago

5 points

345.

MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs

github.com/cpldcpu

8 months ago

5 points

346.

RVVM: RISC-V Virtual Machine

github.com/LekKit

a year ago

5 points

347.

Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code

github.com/micropython

2 years ago

5 points

348.

RedFlag: Leveraging AI to find high security risk code changes

github.com/Addepar

2 years ago

5 points

349.

Ettore: RISC-V virtual machine, written in Go

github.com/teivah

2 years ago

5 points

350.

SERV – The SErial RISC-V CPU

github.com/olofk

3 years ago

5 points

351.

A minimal operating system (2K LOC) on QEMU and a RISC-V board

github.com/yhzhang0128

3 years ago

5 points

352.

core-v-wally: Configurable RISC-V Processor

github.com/openhwgroup

3 years ago

5 points

353.

Show HN: C++17 RISC-V RV32/64/128 userspace emulator library

github.com/fwsGonzo

4 years ago

5 points

354.

T-Head/Alibaba RISC-V CPU cores open sourced

github.com/T-head-Semi

5 years ago

5 points

355.

OpenXiangShan, an open-source high-performance RISC-V processor project

github.com/OpenXiangShan

5 years ago

5 points

356.

Rvemu: RISC-V Emulator written in Rust (browser and CLI)

github.com/d0iasm

5 years ago

5 points

357.

Some Criticisms of RISC-V

gist.github.com

7 years ago

5 points

358.

Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

github.com/darklife

a year ago

4 points

359.

We went from 13 to 48 tools in our trading risk API for AI agents

github.com/System-R-AI

3 months ago

4 points

360.

SERV – The SErial RISC-V CPU

github.com/olofk

2 years ago

peter_d_sherman

4 points