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151.

Show HN: Bronzebeard – Minimal assembler for bare-metal RISC-V development

github.com/theandrew168

5 years ago

7 points

152.

JuiceVM: Smallest RISC-V Virtual Machine that can run Linux mainline kernel

github.com/juiceRv

5 years ago

7 points

153.

BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model

github.com/agra-uni-bremen

2 years ago

6 points

154.

CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux

github.com/openhwgroup

3 years ago

6 points

155.

FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello

github.com/CTSRD-CHERI

5 years ago

6 points

156.

Flute: RISC-V CPU, simple 5-stage in-order pipeline

github.com/bluespec

7 years ago

6 points

157.

RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis

gist.github.com

2 years ago

5 points

158.

Show HN: RISC-V Linux Terminal emulated via WASM

cartesi-machine.surge.sh

3 years ago

5 points

159.

Show HN: Brainfuck to RISC-V JIT compiler written in Zig

github.com/evelance

a year ago

5 points

160.

XiangShan (香山) is an open-source high-performance RISC-V processor project

github.com/OpenXiangShan

5 years ago

5 points

161.

We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V

4 months ago

5 points

162.

MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs

github.com/cpldcpu

8 months ago

5 points

163.

RVVM: RISC-V Virtual Machine

github.com/LekKit

a year ago

5 points

164.

Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code

github.com/micropython

2 years ago

5 points

165.

Ettore: RISC-V virtual machine, written in Go

github.com/teivah

2 years ago

5 points

166.

SERV – The SErial RISC-V CPU

github.com/olofk

3 years ago

5 points

167.

A minimal operating system (2K LOC) on QEMU and a RISC-V board

github.com/yhzhang0128

3 years ago

5 points

168.

core-v-wally: Configurable RISC-V Processor

github.com/openhwgroup

3 years ago

5 points

169.

Show HN: C++17 RISC-V RV32/64/128 userspace emulator library

github.com/fwsGonzo

4 years ago

5 points

170.

T-Head/Alibaba RISC-V CPU cores open sourced

github.com/T-head-Semi

5 years ago

5 points

171.

OpenXiangShan, an open-source high-performance RISC-V processor project

github.com/OpenXiangShan

5 years ago

5 points

172.

Rvemu: RISC-V Emulator written in Rust (browser and CLI)

github.com/d0iasm

5 years ago

5 points

173.

Some Criticisms of RISC-V

gist.github.com

7 years ago

5 points

174.

Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

github.com/darklife

a year ago

4 points

175.

Riscrithm (v1.1) – An intuitive RISC-V assembler and optimizer written in Go

github.com/ghetea-patrick

20 days ago

4 points

176.

SERV – The SErial RISC-V CPU

github.com/olofk

2 years ago

peter_d_sherman

4 points

177.

3ds-CLI, full Linux env on a Nintendo 3ds using RISC V emulation

github.com/cmdada

18 days ago

4 points

178.

Standalone C compiler/assembler/linker/Libc for x86-64/aarch64/riscv64/WASM

github.com/tyfkda

a year ago

4 points

179.

RV64GC Emulator: A RISC-V Emulator developed in C++20

github.com/bane9

3 years ago

4 points

180.

MemPool: Many-core image processor based on RISC-V with Shared L1 cache

github.com/pulp-platform

3 years ago

4 points