HK
Heykuki News
Top
New
Best
Ask
Show
Jobs
Toggle theme
Top
New
Best
Ask
Show
Jobs
Request
1.
▲
Linux-Xlnx – The official Linux kernel from Xilinx
github.com/Xilinx
16 comments
4 years ago
maydemir
41 points
2.
▲
AMD VitisT Al Integrated Development Environment
github.com/Xilinx
discuss
10 months ago
andsoitis
3 points
3.
▲
Xilinx Vitis AI – New Development Stack for AI Inference on Xilinx FPGA and ACAP
github.com/Xilinx
discuss
7 years ago
KenanSulayman
2 points
4.
▲
Xilinx Virtual Cable – debug FPGA/SoC designs without a physical cable
github.com/Xilinx
discuss
11 years ago
unwind
1 points
5.
▲
The Nanotube Compiler and Framework
github.com/Xilinx
discuss
3 years ago
ashvardanian
1 points
6.
▲
An open source Xilinx Spartan 6 miniPCIe development board
github.com/polysome
45 comments
11 years ago
polysome
92 points
7.
▲
How to set up Xilinx Vivado for source control
github.com/jhallen
23 comments
7 years ago
jhallenworld
60 points
8.
▲
NeoApple2: A Port of the Apple2fpga Apple II Emulator to Xilinx FPGAs
github.com/zf3
2 comments
5 years ago
syscall63
54 points
9.
▲
PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP
github.com/regymm
discuss
a year ago
transpute
34 points
10.
▲
Xilinx Virtex 7 FPGA bitstream has been reverse engineered
github.com/SymbiFlow
1 comment
8 years ago
rwmj
14 points
11.
▲
Python Tools for Xilinx Vivado FPGA Projects
github.com/benreynwar
discuss
11 years ago
craigjb
4 points
12.
▲
OpenXC7 – free and open source FPGA toolchain for AMD/Xilinx Series 7 chi
github.com
discuss
a year ago
gjvc
2 points
13.
▲
AIEBLAS: Open-Source Expandable BLAS Implementation for AMD/Xilinx Versal Device
github.com/atlarge-research
discuss
2 years ago
teleforce
1 points
14.
▲
System-Verilog Code for DDR4 Memory Controller with Xilinx Phy (2021)
github.com/oprecomp
discuss
4 years ago
peter_d_sherman
1 points
15.
▲
Xilinx Bitstream Format Library. Easily read .bit files from C programs
github.com/wkoszek
discuss
11 years ago
wkoszek
1 points
16.
▲
Launch HN: Tensil (YC S19) – Open-Source ML Accelerators
87 comments
4 years ago
tdba
96 points
17.
▲
Show HN: An efficient SRL32 (cascading shift registers) clock prescaler in VHDL
gist.github.com
discuss
2 years ago
VioletVillain
2 points
18.
▲
Show HN: A High-Performance CRC Hardware Generator in Bluespec SystemVerilog
github.com/datenlord
discuss
3 years ago
SandmanDZ
2 points